Efficient epoch processing in multichannel global positioning system signal receiver

ABSTRACT

One embodiment of the present invention includes a first memory, an address counter, and an adder. The first memory having KN locations stores K sums of mixer samples during an epoch interval. The mixer samples are generated at a first clock frequency from a mixer for N channels corresponding to N satellites in a global positioning system (GPS) receiver. The address counter generates an address modulo-KN corresponding to a first location in the memory at the first clock frequency. The adder adds one of the mixer samples to contents of the first location to generate a sum. The sum is written into the first location.

RELATED APPLICATION

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/188,883, titled “Low Power Spread-Spectrum ReceiverArchitecture” filed on Mar. 13, 2000.

BACKGROUND

[0002] 1. Field of the Invention

[0003] This invention relates to digital communication. In particular,the invention relates to global positioning system (GPS).

[0004] 2. Description of Related Art

[0005] Global positioning system (GPS) has provided many useful civilianapplications such as in-car navigation systems, automatic positionreporting during emergency, low-visibility harbor operations, navigationsystems for hikers, campers, and other recreational users.

[0006] Existing techniques for designing GPS receivers have a number ofdrawbacks. First, the re-tracking circuit is either complex requiringsignificant amount of hardware, or slow resulting in poor performance.Second, power consumption is high and therefore the receiver is notsuitable for low power applications. Third, the architecture may bedifficult to interface to programmable processors.

[0007] Therefore, there is a need to have an efficient architecture forGPS receivers to process GPS signals efficiently without incurring largepower consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The features and advantages of the present invention will becomeapparent from the following detailed description of the presentinvention in which:

[0009]FIG. 1 is a diagram illustrating a system in which one embodimentof the invention can be practiced.

[0010]FIG. 2 is a diagram illustrating a base-band circuit shown in FIG.1 according to one embodiment of the invention.

[0011]FIG. 3 is a diagram illustrating a multiplier-free demodulatorshown in FIG. 2 according to one embodiment of the invention.

[0012]FIG. 4 is a diagram illustrating a low power passive correlatorshown in FIG. 2 according to one embodiment of the invention.

[0013]FIG. 5 is a diagram illustrating a correlator circuit shown inFIG. 4 according to one embodiment of the invention.

[0014]FIG. 6 is a diagram illustrating the synchronous operation betweenthe circularly shifted data register and the code register shown in FIG.4 according to one embodiment of the invention.

[0015]FIG. 7A is a diagram illustrating a range of correlation resultusing the actual ranges according to one embodiment of the invention.

[0016]FIG. 7B is a diagram illustrating a range of correlation resultusing the represented ranges according to one embodiment of theinvention.

[0017]FIG. 7C is a diagram illustrating a mapping of the correlationresult according to one embodiment of the invention.

[0018]FIG. 8A is a diagram illustrating a pseudo random number generatorand re-tracking circuit shown in FIG. 2 according to one embodiment ofthe invention.

[0019]FIG. 8B is a diagram illustrating a PN code generator shown inFIG. 8A according to one embodiment of the invention.

[0020]FIG. 8C is a diagram illustrating a tap selector shown in FIG. 8Baccording to one embodiment of the invention.

[0021]FIG. 9 is a diagram illustrating a control circuit for PN shiftingaccording to one embodiment of the invention.

[0022]FIG. 10 is a diagram illustrating PN shifting technique as itapplies to one code NCO generator according to one embodiment of theinvention.

[0023]FIG. 11A is a diagram illustrating a Doppler circuit shown in FIG.2 according to one embodiment of the invention.

[0024]FIG. 11B is a diagram illustrating a carrier NCO base circuitshown in FIG. 2 according to one embodiment of the invention.

[0025]FIG. 12 is a diagram illustrating a mixer circuit shown in FIG. 11according to one embodiment of the invention.

[0026]FIG. 13 is a diagram illustrating an epoch processing circuitshown in FIG. 2, which controls the I and Q memory circuits according toone embodiment of the invention.

[0027]FIG. 14 is a diagram illustrating a memory circuit shown in FIG.13 according to one embodiment of the invention.

DESCRIPTION

[0028] In the following description, for purposes of explanation,numerous details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be apparent toone skilled in the art that these specific details are not required inorder to practice the present invention. In other instances, well-knownelectrical structures and circuits are shown in block diagram form inorder not to obscure the present invention.

[0029]FIG. 1 is a diagram illustrating a system 100 in which oneembodiment of the invention can be practiced. The system 100 includes anantenna 110, a radio frequency (RF) front end circuit 120, ananalog-to-digital (A/D) converter 130, a base-band circuit 140, aprocessor 150, and an oscillator 160.

[0030] The system 100 is a receiver system used in to process signalsreceived from a number of satellites in a Global Positioning System(GPS). The antenna 110 receives RF signals transmitted from any one ofthe satellites. The RF front end circuit 120 processes the receivedsignal to convert the signal into an Intermediate Frequency (IF) range.The RF front end circuit 120 may include RF down converters, filters,and amplifiers, etc. The IF analog signal has a frequency range of up to4*f₀ where f₀ is the nominal signal frequency. In one embodiment, f₀ iscompatible with GPS operating frequency ranges. For example, f₀=1.023MHz. As is known by one skilled in the art, any other frequency may beused.

[0031] The A/D converter 130 converts the analog signal from the RFfront end circuit 120 into digital data for digital processing insubsequent stages. The A/D converter 130 operates with a samplingfrequency at 16*f₀. The sampling frequency is selected to provideadequate anti-aliasing without incurring complexity and costs to thesystem 100. A sample-and-hold device (not shown) may be used to hold theanalog signal during the A/D conversion. The sample-and-hold device actslike a sampler operating at the sampling frequency. The word length ofthe A/D converter 130 depends on the characteristics of the signal andthe requirements of the system. In one embodiment, the A/D converter 130has a word size of one bit. When the A/D converter 130 has a word sizeof one bit, it can be implemented as a hard limiter using an operationalamplifier as a comparator. The output of the comparator is one of twologic levels depending on whether the analog sample is greater or belowa predetermined threshold value. The comparator output is the digitizedinput sample and is latched into a flip-flop clocked at a sampling clocksignal. In one embodiment, this sampling clock signal is sixteen timesthe nominal frequency f₀ of 1.023 MHz. The digitized input samples arethen fed to the base-band circuit 140 for base-band processing.

[0032] The base-band circuit 140 is the main section to process thedigitized signal, or samples, to provide correlation results to theprocessor 150. The base-band circuit 140 uses a multi-channelmultiplexing scheme and a spread spectrum architecture. The base-bandcircuit 140 has a number of novel features to be described later. Thesefeatures include efficient processing, simple implementation, and lowpower. The base-band circuit 140 processes the input signal from anumber of satellites in the GPS. In one embodiment, the number ofsatellites is twelve. The base-band circuit 140 employs a parallelmechanism to process all twelve channels corresponding to the twelvesatellites.

[0033] The processor 150 is any processor or processing element that iscapable of executing instructions and communicating with input/outputdevices or circuits. The processor 150 generates control information tothe base-band circuit 140 and interfaces to input/output devices orelements. The input/output devices or elements may include any suitableinput/output. Examples of the input/output devices or elements includeuser's keyboard, display, serial communication interface, and parallelinput/output processor. The processor 150 may include a centralprocessing unit (CPU), a memory, and any appropriate interfacingdevices. Examples of the CPU include general-purpose microprocessorswith any architecture (e.g., superscalar, vector processor, reducedinstruction set computer), micro-controllers, digital signal processors,embedded processors.

[0034] The oscillator 160 provides a basic clock signal to the base-bandcircuit 140. The basic clock signal is then divided into many clocksignals having various frequencies compatible with the GPS timings. Inone embodiment, the basic clock signal has a frequency of 48*f₀. Thebase-band circuit 140 derives other clock signals using the basic clocksignal. These clock signals are used to synchronize the elements and/ordevices in the base-band circuit 140. The base-band circuit 140 alsoprovides clock and/or timing signals to the RF front end circuit 120.

[0035]FIG. 2 is a diagram illustrating the base-band circuit 140 shownin FIG. 1 according to one embodiment of the invention. The base-bandcircuit 140 includes a multiplier-free demodulator 220, a low-powerpassive correlator 230, a pseudo random number (PN) generator andre-tracking circuit 240, a Doppler circuit 250, an epoch processingcircuit 260, and a clock generator 270.

[0036] The multiplier-free demodulator 220 is a base-band down converterto bring the signal to zero IF. This is accomplished by multiplying theinput samples with sine and cosine of angles differing by 90° to splitinto in-phase (I) and quadrature (Q) components. In one embodiment, thesignal is over sampled at a sampling frequency that is 4q (where q is aninteger) times higher than the signal frequency. An efficient mixer isused to replace the multiplier by an equivalent operation. Then, theresulting samples are decimated to keep the samples within a desiredfrequency range.

[0037] The low-power passive correlator 230 correlates the decimatedsamples from the multiplier-free demodulator 220 with PN code samples,which are locally generated. The passive correlator 230 is a de-spreaderto recover the transmitted signal samples at the proper frequency range.The PN code samples are part of a PN sequence. In one embodiment, the PNsequence has a length of 1023. The passive correlator 230 works with twophases per chip and checks blocks of 2N phases for synchronization forall K satellite channels. N is an integer selected so that the PNsequence can be processed over a multiple of times. Possible values forN to allow an evenly divisible number of times from the PN sequencelength of 1023 are N=3, 11, and 31. The values 1023, 3, 11, and 31 arefor illustrative purposes only. The choice of 3 provides a very shortturn-off time. The choice of 31 increases the hardware complexity. Thechoice of 11 is a compromise between hardware complexity and turn-offtime. As is known by one skilled in the art, any other numbers can beused. Correlation between the data samples and the PN code samplestypically involves shifting operations to shift the data samples and thePN code samples in synchrony. Each time new samples are shifted in amultiplication is performed on the newly shifted samples to produce aproduct. For a block of N samples, there are N products. Thereafter, anaddition is performed on the N products to produce a correlation resultfor that block. The passive correlator 230 reduces power consumptioncaused by shift registers by using a multiplexing data writingtechnique. In addition, the multiplication and addition are muchsimplified to keep the correlation result within a small number of bits.In one embodiment, the correlation result or output of the passivecorrelator 230 is 6-bit including a sign bit.

[0038] The pseudo random number (PN) generator and re-tracking circuit240 generates the PN code samples to the passive correlator 230. Todistinguish various satellites, a unique PN code is assigned to eachsatellite. These codes are chosen for maximum orthogonality to maximizedetectability. The PN code samples are generated for N satellitessequentially. The generation of the PN code samples is clocked by anumerically controlled oscillator (NCO). For re-tracking, the NCO canadvance or slip over a number of chips. The number of chips advanced orslipped may be any number. In one embodiment, this number ranges from 0to 5.5 (e.g., 1, 2, 3, 4, 5, or 5.5). The PN generator and re-trackingcircuit 240 is controlled by the processor 150. The processor 150determines how many chips the PN code have to be shifted and loads anappropriate number into the PN generator and re-tracking circuit 240 anda shift command.

[0039] The Doppler circuit 250 removes the Doppler shifts on thecorrelation outputs from the passive correlator 230. This is performedby another mixer circuit to mix the de-spreaded samples with the sineand cosine values provided by a carrier NCO for a selected satellite.For N satellites, N carrier NCO's are used. The Doppler circuit 250sequences through the N carrier NCO's.

[0040] The epoch processing circuit 260 processes the data at the end ofeach epoch. At the end of each epoch, the PN code samples are filledwith all 1's. The epoch processing circuit 260 sequences through the Nsatellite channels. The result samples are accumulated or added toprovide final result for each satellite. A double-buffered memory schemeis used to allow storing one set of samples in a first memory while aset of results is read out to a second memory. The processor 150 thencan access the second memory to retrieve the results for furtherprocessing.

[0041] The clock generator 270 generates various clock signals to beused by other circuits in the base-band circuit 140. In one embodiment,the clock generator 270 receives the basic clock signal at 48 times thenominal frequency f0. From this basic clock signal, the clock generator270 generates all or a subset of the following clock signals: a samplingclock signal at 24*f₀, a clock signal at 16*f₀, a clock signal at 8*f₀,a clock signal at 4*f₀, and a clock signal at 2*f₀. The clock generator270 may be implemented by a number of methods. One method is to use acounter clocked by the basic clock signal and some logic gates. Theoutputs of the counter are the divide-by-K clock signals that havefrequencies of 24*f₀, 16*f₀, 8*f₀, 4*f₀, and 2*f₀. To prevent clockskewing, additional delay elements may be inserted as appropriate.

[0042]FIG. 3 is a diagram illustrating the multiplier-free demodulator220 shown in FIG. 2 according to one embodiment of the invention. Thedemodulator 220 includes a gating circuit 310, a demultiplexer 320, anintegrator/decimator 330, a mapper 340, and a reset circuit 350.

[0043] The gating circuit 310 essentially performs a multiplication ofthe input samples with the sine and cosine values without using anactual multiplier. As discussed earlier, the input samples are one-bitsamples clocked at the sampling clock signal having a frequency of16*f₀. The input samples are then multiplied by two-bit sine and cosinevalues at 4*f₀. This multiplication is equivalent to multiplication bytwo consecutive +1's and two −1's. Furthermore, since the input samplesare one-bit having logic values of 0 and 1, the multiplication can beefficiently performed by an exclusive OR operation. The gating circuitincludes an exclusive OR gate 312 and a frequency divider 314. Theexclusive OR gate 312 performs the multiplication between the inputsamples and the sine/cosine values of two consecutive +1's and two −1's.The sine and cosine values can be encoded as +1's and 0's. The frequencydivider 314 generates the sine/cosine values of +1's and 0's. Thefrequency divider 314 can be implemented as two flip-flops connected incascade to effectively divide the sampling clock by four to provide aclock signal having a frequency of 4*f₀. The frequency divider 314 alsogenerates two complementary clock signals at frequency of 8*f₀: one istrue form and one is in complementary form. These two complementary 8*f₀clock signals are used by the demultiplexer 320. The gating circuit 314generates a gated input sample at the frequency of the sampling clocksignal.

[0044] The demultiplexer 320 essentially splits the mixed input samplesinto in-phase and quadrature components. This is performed bydemultiplexing the gated input sample into two signals. Thedemultiplexer 320 includes two synchronizers 322 and 324. Thesynchronizers 322 and 324 synchronizes the gated input sample by thetrue and complementary form of the 8*f₀ clock signal, respectively, togenerate the in-phase and quadrature samples. Since the synchronizers322 and 324 are clocked by the 8*f₀ clock signal, they essentially downsample the gated input samples at 8*f₀ frequency by a factor of two.

[0045] The integrator/decimator 330 further down samples or decimatesthe in-phase and quadrature samples by integrating them in anintegration interval. The integration interval is selected to beequivalent to a four-sample interval so that the down sampling bring thegated input samples to 2*f₀ samples/sec. This can be done effectively bycounting the number of l's in the gated input sample in a 4-sampleinterval. The integrator/decimator 330 includes two K-bit counters 332and 334 to count the number of 1's in the in-phase and quadraturesamples from the synchronizers 322 and 324, respectively. The K-bitcounters 332 and 334 are reset by a reset signal generated from thereset circuit 350. This reset signal is to start a new integrationinterval. The K-bit counters 332 and 334 generate in-phase andquadrature decimated samples, respectively, to the mapper 340. K isselected to ensure that the count value can cover the possible range ofnumbers. Note that the in-phase or quadrature sample is one-bit.Therefore, the possible numbers of bit 1's in the in-phase or quadraturesample in a 4-sample integration interval are 0, 1, 2, 3, and 4. If +1'sand −1's are used to encode the integrated samples, these numbers areequivalent to −2, −1, 0, +1, and +2. To represent these numbers, K wouldhave been 3. In other words, the effect of down sampling is that eachsample becomes a three-bit sample.

[0046] The mapper 340 maps the in-phase and quadrature decimated samplesinto in-phase and quadrature demodulated samples, respectively. Thein-phase and quadrature demodulated samples have L bits where L is lessthan K. This mapping reduces the number of bits to represent thein-phase and quadrature decimated samples for more efficient processing.This mapping acts like a lower and upper hard limiter on the {0, 1, 2,3, 4} range to limit the lower value to 1 and the upper value to 3. Inother words, 0 and 1 are mapped into 1, 2 is mapped into 2, 3 and 4 aremapped into 3. The mapper 340 includes two combinational circuits 342and 344 to perform this mapping for the in-phase and quadraturedecimated samples, respectively. The three input A, B, and C of thedecimated samples are mapped into two outputs BN and CN as shown in FIG.3. The two-bit in-phase and quadrature demodulated samples are fed tothe passive corrrelator 230 for further processing.

[0047] The reset circuit 350 resets the integrator/decimator 330 at theend of each integration interval. The reset circuit 350 includes anM-bit counter 362 and an OR gate 364.

[0048] The M-bit counter 362 is clocked by the true form of the 8*f₀clock signal and is reset by a system reset signal. The M-bit counter362 generates a terminal count signal when the maximum count is reached.The OR gate 364 performs an OR operation between the terminal countsignal of the M-bit counter 362 and the reset signal. When the resetsignal or the terminal count signal is asserted, the reset circuit 350asserts the reset signal to reset both the K-bit counters 332 and 334 inthe integrator/mapper 330. M is selected to correspond to theintegration interval. In one embodiment, the integration interval isequivalent to 4-sample interval and M is equal to 2.

[0049]FIG. 4 is a diagram illustrating the low power passive correlator230 shown in FIG. 2 according to one embodiment of the invention. Thepassive correlator 230 includes a load register 410, a circular shiftregister 420, a correlator circuit 430, a code register 440, N storageelements 452 ₁ to 452 _(N), and a write circuit 460. Note that forsimplicity, only one passive correlator is shown. For completeness, twopassive correlators are used to process the in-phase and quadraturecomponents.

[0050] The load register 410 receives the two-bit in-phase andquadrature demodulated samples from the demodulator 220. The loadregister 410 transfers its contents to the circular shift register 420at a clock rate equivalent to 2*f₀/M where M is the number ofdemodulated samples to be stored in the load register 410. In oneembodiment, the load register 410 has twenty-two elements (or M=22) tostore a block of 11 samples of two phases. The selection of the number11 is explained above. The load register 410, therefore, is organized tostore a total of forty-four bits. For a nominal value of f₀=1.023 MHz,the transfer rate from the load register 410 to the circular shiftregister 420 is 93 KHz or a period of 10.75 μsec.

[0051] The circular shift register 420 circularly shifts a demodulatedsample into a data position at the 2*f₀ clock rate. In one embodiment,the shift is left shift and circular in that the leftmost sample isshifted into the rightmost position.

[0052] The correlator circuit 430 computes a correlation result from thedemodulated samples and the code samples provided by the code register440. During the 2*f₀ clock period, the correlator circuit 430 computescorrelation results for twelve satellites.

[0053] The code register 440 stores M PN code samples transferred fromone of the N storage elements 452 ₁ to 452 _(N). The N storage elements452 ₁ to 452 _(N) store N PN code sequences corresponding to Nsatellites. All N storage elements 452 ₁ to 452 _(N) operate insynchrony. The N PN code sequences come from the PN generator andre-tracking circuit 240 (FIG. 2). The writing of the N PN code samplesinto the N storage elements 452 ₁ to 452 _(N) is synchronized with thecircular shifting of the circular shift register 420 so that correctphase values are correlated with correct code samples. For each storageelement, a code sample is written into the storage element at a codeposition corresponding to a data position of the correspondingdemodulated sample in the circular shift register 420. This writing isessentially equivalent to shift the N storage elements 452 ₁ to 452 _(N)synchronously with the circular shifting of the circular shift register420. By avoiding using N shift registers to shift N PN code sequences,significant reduction of power consumption is achieved. The synchronousoperation between the circular shift register 420 and the N storageelements 452 ₁ to 452 _(N) is explained more in FIG. 6. The N storageelements 452 ₁ to 452 _(N) may be implemented as N rows of flip-flopswhere each row has M flip-flops, N registers with selectable data write,or N rows of a static random access memory (RAM), or any other suitablestorage devices.

[0054] The write circuit 460 writes N code samples into the N storageelements 452 ₁ to 452 _(N) at the N code positions corresponding to thedata position of the circular shift register 420. The write circuit 460includes a decoder 470 to enable the N code positions for writingsynchronously with the shifting of the circular shift register 420. Ifeach of the N storage elements 452 ₁ to 452 _(N) is implemented by Mflip-flops, the decoder 470 essentially enables the gating of the clocksignal that clocks the flip-flops.

[0055] After a short turn-off time, the passive correlator 230 allowsfor re-tracking in principle within 10.75 μs if the PN code has driftedaway +/−5.5 chips. That is equivalent to about 5.5 μs change in onepseudo range. Assuming 300,000 km/s speed of light that corresponds to asatellite moving 1.67 km toward or away from the receiver, and assumingthat the speed of a satellite is 3 km/s, then under worst-caseconditions without further signal processing, it is possible to turn offthe receiver for 0.5 second. This turn-off time results in a largereduction of power consumption. In reality, the correlator output has tobe integrated over many cycles to be valid. The satellite movement alsofollows certain predictable paths. It is then possible despite themultiple integration requirement to keep the GPS unit turn off for manyseconds.

[0056]FIG. 5 is a diagram illustrating the correlator circuit 430 shownin FIG. 4 according to one embodiment of the invention. The correlatorcircuit 430 includes M mappers 510 ₁ to 510 _(M), an adder 520, asubtractor 530, and a register 540.

[0057] The M mappers 510 ₁ to 510 _(M) map the M two-bit demodulatedsamples and the corresponding M one-bit code samples in the coderegister 440 to generate M two-bit mapper outputs. The mapping isessentially equivalent to a multiplication of the demodulated samplewith the code sample. In addition, the mapping also provides a properbit representation for the data to simplify the implementation. Each ofthe M mappers 510 ₁ to 510 _(M) is implemented by a combinationalcircuit including an exclusive-OR gate, an OR gate, and an inverter asshown in FIG. 5. This mapping is further explained in FIGS. 7A through7C.

[0058] The adder 520 adds the M two-bit mapper outputs to generate aresult sum. The subtractor 530 subtracts a bias value from the resultsum to generate the correlation result. The register 540 stores thecorrelation result at the sampling clock rate.

[0059]FIG. 6 is a diagram illustrating the synchronous operation betweenthe circularly shifted data register and the code register shown in FIG.4 according to one embodiment of the invention.

[0060] At time t, the circular shift register 420 is parallel loadedwith 11 pairs of demodulated samples. Each pair includes two phases aand b. The 22 samples are (a_(n), b_(n)), (a_(n+1), b_(n+1)), . . . ,(a_(n+10), b_(n+10)). At the same time, the code register 440 is loadedwith the corresponding 11 pairs of code samples from one of the Nstorage elements 452 ₁ to 452 _(N). The 22 code samples are (s_(m),t_(m)), (s_(m+1), t_(m+1)), . . . , (s_(m+10), t_(m+10)).

[0061] At time t+Δt, the circular shift register 420 circularly shiftsthe 22 samples so that each sample is shifted to the left and the leftmost sample b_(n+10) is shifted to occupy the rightmost position. At thesame time, the writing circuit 460 (FIG. 4) writes to the rightmostposition of the N storage elements 452 ₁ to 452 _(N). Then the coderegister is loaded with one of the N storage elements 452 ₁ to 452 _(N).Note that the code register 440 is loaded with contents of all the Nstorage elements corresponding to the N satellites within the Δt timeinterval. The remaining code samples remain the same.

[0062] At time t+2 Δt, the circular shift register 420 circularly shiftsthe 22 samples so that each sample is shifted to the left and the leftmost sample a_(n+10) is shifted to occupy the rightmost position. At thesame time, the writing circuit 460 (FIG. 4) writes to the next rightmostposition of the N storage elements 452 ₁ to 452 _(N). Then the coderegister is loaded with one of the N storage elements 452 ₁ to 452 _(N).The remaining code samples remain the same. The process continues whenall M code samples are written into the N storage elements 452 ₁ to 452_(N). At time t+kΔt, N code samples are written into the code position kwhile the other code positions contain the same code samples.Thereafter, a new sequence of M demodulated samples is transferred tothe circular shift register 420 and the process repeats.

[0063] By using N storage elements 452 ₁ to 452 _(N) and a cleverwriting mechanism, it is not necessary to use N shift registers. Thisresults in a significant reduction of power consumption.

[0064]FIG. 7A is a diagram illustrating a range of correlation resultusing the actual ranges according to one embodiment of the invention. Inthis illustrative example, M=22 corresponding to two phases of the 11samples.

[0065] The demodulated sample may be one of −1, 0, and +1 values. The PNcode sample may be one of −1 and +1. When multiplied together, theproduct may be one of −1, 0, and +1 result. When added together, the 22products may form a sum having a range of {−22, +22}.

[0066]FIG. 7B is a diagram illustrating a range of correlation resultusing the represented ranges according to one embodiment of theinvention.

[0067] The demodulated samples are encoded to have representations of01, 10, and 11, corresponding to −1, 0, and +1, respectively. The PNcode sample is represented by 0 and 1, corresponding to −1 and +1,respectively. The mapper M maps the product to 1, 2, and 3,corresponding to −1, 0, and +1, respectively. The adder produce a sum inthe range of {+22, +66}. The subtractor subtracts a bias value of 22from the sum so that the result has a range of {0, +44}. This range canbe represented by a 6-bit result.

[0068]FIG. 7C is a diagram illustrating a mapping of the correlationresult according to one embodiment of the invention.

[0069] The mapping is equivalent to a multiplication of −1, 0, +1 and−1, +1. The mapping implements the following multiplication table. Datasample Code sample Product 01 (−1) 0 (−1) 01 (+1) 01 (−1) 1 (+1) 11 (−1)10 (0) 0 (−1) 10 (0) 10 (0) 1 (+1) 10 (0) 11 (+1) 0 (−1) 11 (−1) 11 (+1)1 (+1) 01 (+1)

[0070] Note that the values inside parentheses represent the actualvalues. Other mappings are possible. The mapping can be implemented by acombinational circuit for the mapper shown in FIG. 5.

[0071]FIG. 8A is a diagram illustrating the pseudo random number (PN)generator and re-tracking circuit 240 shown in FIG. 2 according to oneembodiment of the invention. The PN generator and re-tracking circuit240 includes a control circuit 810, N accumulators 820 ₁ to 820 _(N), Nincrement registers 830 ₁ to 830 _(N) and a PN generator 840.

[0072] The control circuit 810 generates at least a channel enablesignal based on control information from the processor 150 (FIG. 1) atthe 8*f₀ frequency. For N satellites, the control circuit 810 generatesN channel enable signals. The control information includes at least oneof channel select information, an initial count, an increment value, andPN command.

[0073] Each of the N accumulators 820 ₁ to 820 _(N) generates a PN clocksignal corresponding to the selected satellite channel based on theincrement value. The PN clock signal is used by the PN generator 840.Each of the N accumulators 820 ₁ to 820 _(N) is enabled by acorresponding channel enable signal from the control circuit 810.

[0074] Each of the N increment registers 830 ₁ to 830 _(N) stores anincrement value of the corresponding satellite channel at the 8*f₀frequency. The processor 150 selects a satellite channel by writing thechannel select information and writes the increment value to theselected channel. In one embodiment, each of the N increment registers830 ₁ to 830 _(N) has 16 bits.

[0075] The PN generator 840 generates N PN code samples to the passivecorrelator 230 based on the channel select information. As discussedearlier, each of the N satellites has a unique PN code sequence. Duringnormal operation, the PN generator 840 operates at the nominal f0frequency. During re-tracking, the PN codes are shifted back and forthbased on the individual PN clock signals provided by the N accumulators820 ₁ to 820 _(N). The PN generator 840 includes N PN code generators845 ₁ to 845 _(N) clocked by the PN clock signals from N accumulator 820₁ to 820 _(N), respectively.

[0076]FIG. 8B is a diagram illustrating the PN code generator 845 _(k)shown in FIG. 8A according to one embodiment of the invention. The PNcode generator 845 _(k) includes a G1 coder 850, a G2 coder 860, an ANDgate 865, a tap selector 870, and an exclusive OR gate 875.

[0077] The G1 coder 850 generates a G1 code sequence. The G1 coder 850includes a shift register 852 and an exclusive OR gate 854. The shiftregister 852 has ten elements and shifts the code bits to the right. Theshift register 852 is clocked by the PN clock signal k from thecorresponding accumulator 820 _(k) (FIG. 8A). The processor 150initially loads the shift register 852 with all 1's. The exclusive ORgate 854 is a two-input exclusive OR gate which perform an exclusive ORoperation on elements 3 and 10 of the shift register 852. The output ofthe exclusive OR gate goes back to the input of the shift register 852.

[0078] The G2 coder 860 includes a shift register 862 and an exclusiveOR gate 864. The shift register 862 has ten elements and shifts the codebits to the right. The shift register 862 is clocked by the PN clocksignal k from the corresponding accumulator 820 _(k) (FIG. 8A). Theprocessor 150 initially loads the shift register 862 with all 1's. Theexclusive OR gate 864 is a six-input exclusive OR gate which perform anexclusive OR operation on elements 2, 3, 6, 8, 9, and 10 of the shiftregister 862. The output of the exclusive OR gate 864 goes back to theinput of the shift register 862.

[0079] The AND gate 865 is a ten-input AND gate which performs an ANDoperation on all ten elements of the shift register 862. When all theten elements of the shift register 862 contain all 1's, an epoch eventhas occurred, i.e., an epoch is ended and a new epoch begins. The outputof the AND gate 865, therefore, provides an indication that an epoch haselapsed. This epoch event signal is used by the epoch control circuit inthe epoch processing circuit 260 (FIG. 6).

[0080] The tap selector 870 selects the taps in the shift register 862of the G2 coder 860 to be used in generating the PN code k out of the PNgenerator 840 (FIG. 8A). The selected taps in the shift register 862 areunique for each satellite. The processor 150 writes the selection to thetap selector 870.

[0081] The exclusive OR gate 875 performs an X-OR operation on theoutput of the G1 coder 850 and the output of the tap selector 870 togenerate the PN code k.

[0082]FIG. 8C is a diagram illustrating the tap selector 870 shown inFIG. 8B according to one embodiment of the invention. The tap selector870 includes a tap register 875, a mask circuit 880, and an exclusive ORgate 890.

[0083] The tap register 875 has ten elements corresponding to the tenelements of the shift register 862 in the G2 coder 860. The tap register875 is written by the processor 150 to select the P taps unique to asatellite. In one embodiment, P=2. The mask circuit 880 masks thenon-selected taps from the shift register 862 using the tap register875. The mask circuit 880 includes ten AND gates 8851 to 88510. Each ofthe AND gate ANDs a cell of the tap register 875 with a correspondingcell of the shift register 862. If any of the cells of the G2 coder 860are selected, those cells are tapped into the exclusive OR gate 890. Theoutput of the X-OR gate 890 goes to the exclusive OR gate 875.

[0084]FIG. 9 is a diagram illustrating the control circuit 810 for PNshifting technique as it applies to one code NCO generator according toone embodiment of the invention. The control circuit 810 includes adecoder 910, a channel enable register 920, a counter 930, and a logiccircuit 940.

[0085] The decoder 910 receives the channel select information from theprocessor 150 (FIG. 1) and generates N decoded signals from the channelselect information. For N=12, the decoder 910 is a 4-to-12 decoder. Thechannel enable register 920 stores the decoded signals to generate Nchannel enable signals at a 8*f0 frequency. The loading of the channelenable register 920 is enabled by the logic circuit 940. The channelenable register 920 is asynchronously reset by the logic circuit 940.

[0086] The counter 930 updates a count for the amount of PN shiftingrequired from the initial count at the 8*f₀ clock signal. When the countreaches a terminal count, the counter 930 generates a terminal signal toreset the channel enable register 920. In one embodiment, the counter930 is an 8-bit down counter to count from the initial count to zero,i.e., the terminal count is zero. The processor 150 writes the initialcount to the counter 930.

[0087] The logic circuit 940 generates a load signal and a reset signal.The load signal is to load the counter 930 and the channel enableregister 920. The reset signal is to reset the channel enable register920.

[0088]FIG. 10 is a diagram illustrating the PN shifting technique as itapplies to one code NCO generator according to one embodiment of theinvention. The accumulator 820 includes an accumulating register 1010,an adder 1020, and an adder control circuit 1030.

[0089] The accumulating register 1010 stores a NCO value at a currentcycle of the 8*f₀ clock signal. The NCO value provides the PN clocksignal for the selected satellite channel. In one embodiment, theaccumulating register 1010 has 28 bits and the most significant bit ofthe NCO value provides the PN clock signal.

[0090] The adder 1020 adds the increment value from the correspondingincrement register to the NCO value from the accumulating register 1010to generate a sum representing the NCO value loaded into theaccumulating register 1010 in the next clock cycle of the 8*f₀ clocksignal.

[0091] The adder control circuit 1030 is a combinational circuit togenerate an enable command, a left shift command, and a right shiftcommand to the adder 1020 using the PN command provided by the processor150 and the channel enable signal from the channel enable register 920(FIG. 9). When the channel enable signal is de-asserted indicating thesatellite channel is not selected, the adder control circuit asserts theenable command which asserts bit 25 of the adder 1020. The bit 25 isselected to correspond to a value 225 which is increment correspondingto the PN generator frequency of 1.023 MHz. When the channel enablesignal is asserted indicating the satellite channel is selected, theadder control circuit 1030 asserts a left command when the shift commandis LOW and asserts a right command when the shift command is HIGH. Theleft and right commands assert bits 24 and 26, respectively.

[0092] The accumulator 820 overflows at the required frequency of f_(g).In one embodiment, the most significant bit (MSB) of the accumulatoroutput is a square wave of f_(g) frequency. Let n=28 and m=16 be thenumber of bits for the accumulating register and the increment value.Let M be the marching value. Let f_(c)=8*f₀ where f₀=1.023 MHz. Then:

f _(g) =Mf _(c)/2^(n)  (1)

f _(g)=1.023×10⁶ Hz=M*8*(1.023×10⁶ Hz)/2²⁸  (2)

→M=2 ²⁵  (3)

[0093] If the frequency fg is advanced by adding to the marching value,then the time it takes to advance by q chips can be calculated asfollows.

q=[(M+ΔM)*f _(c)/2^(n) −M*f _(c)/2^(n) ]*t  (4)

t=q/{ΔM*f _(c))/2^(n)=(q/f _(g))*(M/ΔM)Δtm (5)

[0094] Using the above equations, the time and the number of NCO clockcycles needed to advance or slip up to +/−5.5 chips can be calculated asfollows:

f _(c)8*f ₀=8.184 MHz, m=16, n=28, M=2²⁵

[0095] For f_(g)=1.023 MHz: Number of chips advanced T (μs) NCO clockcycles 1 0.977  8 2 1.955 16 3 2.932 24 4 3.910 32 5 4.887 40 5.5 5.37644

[0096] For f_(g)=2*1.023 MHz: Number of chips slipped T (μs) NCO clockcycles 1 1.955 16 2 3.910 32 3 5.065 48 4 7.820 64 5 9.770 80 5.5 10.7588

[0097] The NCO marching value can be used to advance or slip preciselyto within +/−5.5 chips by counting the number of NCO clock cycles allwithin less than 11 μs. It is also possible to totally sty the NCO clockfor a number of cycles to compensate for the slippage.

[0098]FIG. 11A is a diagram illustrating the Doppler circuit 250 shownin FIG. 2 according to one embodiment of the invention. The Dopplercircuit 250 includes a carrier NCO 1110, a look up table 1120, tworegisters 1125 and 1127, and a mixer circuit 1110.

[0099] The carrier NCO generates a carrier NCO value to select sine andcosine values from the look up table 1120. The carrier NCO includes adecoder 1112, N carrier NCO base circuits 1114 ₁ to 1114 _(N), amultiplexer 1116, and a counter 1118. The decoder 1112 generates decodedsignals from the channel select information. The decoded signalscorrespond to the satellite channels. Each of the carrier NCO basecircuits 1114 ₁ to 1114 _(N) provides a carrier NCO value correspondingto the selected satellite channel. In one embodiment, the carrier NCOvalue is 3-bit. The multiplexer 1116 selects one of the 3-bit N carrierNCO values based on the select signal generated by the counter 1118. Thecounter 1118 sequences through the N channels and clocked by thesampling clock signal at 24*f₀ frequency.

[0100] The look up table 1120 generates the coefficients based on thecarrier NCO value. The coefficients include the sine and cosine valuesto be used by the mixer circuit 1130. In one embodiment, the sine andcosine values are stored in the look up table 1120 according to the3-bit carrier NCO values as follows. Carrier NCO value Sine value Cosinevalue 000 000 (0) 011 (3) 001 010 (2) 010 (2) 010 011 (3) 000 (0) 011010 (2) 110 (−2) 100 000 (0) 111 (−3) 101 110 (−2) 110 (−2) 110 111 (−3)000 (0) 111 110 (−2) 010 (2)

[0101] the two registers 1125 and 1127 store the sine and cosine valuesfrom the look table 1120 at the sampling clock signal of 24*f₀frequency.

[0102] The mixer circuit 1130 mixes the demodulated sample from thepassive correlator 230 (FIG. 2) with the coefficients (e.g., the sineand cosine values) from the look up table 1120 to generate a mixersample. The mixer sample includes a mixer in-phase sample and a mixerquadrature sample. The mixer circuit 1130 includes mixer in-phase andquadrature circuits 1132 and 1334 to generate the mixer in-phase andquadrature samples, respectively.

[0103]FIG. 11B is a diagram illustrating the carrier NCO base circuit1114 shown in FIG. 2 according to one embodiment of the invention. Thecarrier NCO base circuit 1114 includes a carrier increment register1140, an adder 1150, and a carrier accumulating register 1160.

[0104] The carrier increment register 1140 stores a carrier incrementvalue provided by the processor 150 at a f₀/4 frequency. The adder 1150adds the carrier increment value the carrier NCO value stored in theaccumulating register 1160 to produce a sum. The sum is then stored inthe accumulating register 1160. The accumulating register 1160 storesthe sum generated by the adder 1150 at a f₀/4 frequency.

[0105]FIG. 12 is a diagram illustrating the mixer circuit 1130 shown inFIG. 11 according to one embodiment of the invention. The mixer circuit1130 includes a mixer in-phase circuit 1210 and a mixer quadraturecircuit 1220.

[0106] The mixer in-phase circuit 1210 generates an in-phase mixersample I_(m) from the in-phase and quadrature demodulated samples I_(d)and Q_(d) as follows:

I _(m) =I _(d)*cos−Q _(d)*sin  (6)

[0107] The mixer quadrature circuit 1210 generates a quadrature mixersample Q_(m) from the in-phase and quadrature demodulated samples I_(d)and Q_(d) as follows:

Q _(m) =I _(d)*sin+Q _(d)*cos  (7)

[0108] where sin and cos are the sine and cosine values provided by thetwo registers 1125 and 1127, respectively. The I_(m) and Q_(m) are theresults of complex multiplications between the I_(d), Q_(d) with thesine and cosine values.

[0109] The mixer in-phase circuit 1210 includes two logic circuits 1212and 1214 and an adder 1216. Each of the logic circuits 1212 and 1214essentially performs a multiplication between the 6-bit demodulatedsample and the sine or cosine value to generate an 8-bit productconsidering the range of value at the input and output and the codingmethod used. The multiplexer is a simplified set of logic gates. Theadder 1216 adds the two 6-bit products to provide the in-phase mixersample according to equation (6). The mixer quadrature circuit 1220includes two logic circuits 1222 and 1224 and an adder 1226. The twologic circuits 1222 and 1224 are the same as the logic circuits 1212 and1214. The adder 1226 adds the two 6-bit products to provide thequadrature mixer sample according to equation (7).

[0110]FIG. 13 is a diagram illustrating the epoch processing circuit 260shown in FIG. 2 which controls the I and d memory circuits according toone embodiment of the invention. The epoch processing circuit 260includes in-phase and quadrature memory circuits 1310 and 1320, an epochcontrol circuit 1330, and a multiplexer 1340.

[0111] Each of the in-phase and quadrature memory circuits 1310 and 1320accumulates the corresponding mixer samples over an epoch interval. Thein-phase and quadrature memory circuits 1310 and 1320 are essentiallyidentical except that the input for the in-phase memory circuit 1310 isthe mixer in-phase sample and the input to the quadrature memory circuit1320 is the mixer quadrature sample. The epoch control circuit 1330generates an epoch control signal to the in-phase and quadrature memorycircuits 1310 and 1320 indicating an end of an epoch. The multiplexer1340 selects one of the in-phase and quadrature memory circuits 1310 and1320 to be read by the processor 150.

[0112]FIG. 14 is a diagram illustrating the memory circuit 1310 shown inFIG. 13 according to one embodiment of the invention. The memory circuit1310 includes an accumulating memory 1410, four registers 1412, 1414,1425, and 1435, an address counter 1420, an adder 1430, a buffer memory1440, a register 1445, and a gating circuit 1450.

[0113] The accumulating memory 1410 stores P sums of the mixer samplesduring an epoch interval as provided by the epoch control circuit 1330(FIG. 13). The mixer samples arrive at the accumulating memory 1410 atthe sampling clock frequency of 24*f₀, or every 40.72 nsec for a nominalfrequency fo of 1.023 MHz. Each block of mixer samples includes thecomplex mixing of the 22-phase block of the input samples and the22-phase block of the PN code samples. For the entire epoch intervalwhich corresponds to 1023/11=93 blocks of 22-phase blocks of the inputsamples, the accumulation essentially adds the 22-phase result blocksfor 93 times. The value of the mixer samples has a range of {−88, +88}.The range of the epoch result is therefore equal to +/−88×93=+/−8184.This range requires a word size of 14 bits including the sign bit. Eachepoch also involves 12 satellite channels. To accumulate 22-blocks forall 12 channels, the total number of epoch values stored in theaccumulating memory 1410 is 264. The accumulating memory 1410 istherefore organized as 512×16 to accommodate 264×14 epoch results. Inone embodiment, the accumulating memory 1410 is implemented as adual-ported memory to allow simultaneous read and write. This allowsreading the partial sum from the accumulating memory 1410 and writingthe partial sum to the accumulating memory 1410 at the same address atthe same time.

[0114] The address counter 1420 generates an address to the accumulatingmemory 1410 and the buffer memory 1440. The address counter 1420 isclocked by the sampling clock signal of 24*f₀ frequency. The addresscounter 1420 sequences through the 12 satellite channels and the 22phases. Therefore, the address counter 1420 generates the address modulo12×22=264.

[0115] The adder 1430 adds a mixer sample to the sum stored in theaccumulating memory 1410. The result of the adder 1430 is written to theaccumulating memory 1430. This result is read out in the next cycle tocontinue accumulating the mixer samples over the epoch interval.

[0116] The buffer memory 1440 stores the P sums transferred from theaccumulating memory 1410 at the end of each epoch interval. The contentsof the buffer memory 1440 are read by the processor 150 via themultiplexer 1340. In one embodiment, the buffer memory 1440 is adual-ported memory to allow simultaneous writing and reading.

[0117] The registers 1412, 1414, 1425 and 1435 are clocked by thesampling clock signal at 24*f₀ frequency to synchronize the latching ofthe address and data for the accumulating and buffer memories 1410 and1440.

[0118] The register 1445 synchronizes the epoch control signal with thesampling clock signal at 24*f₀ frequency. The gating circuit 1450 gatesthe partial sum from the accumulating memory 1410 with the epoch controlsignal so that when the accumulating memory 1410 is in the write mode,the buffer memory 1440 is available for read and vice versa.

[0119] While this invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications of the illustrativeembodiments, as well as other embodiments of the invention, which areapparent to persons skilled in the art to which the invention pertainsare deemed to lie within the spirit and scope of the invention.

What is claimed is:
 1. An apparatus comprising: a first memory having KNlocations to store K sums of mixer samples during an epoch interval, themixer samples being generated at a first clock frequency from a mixerfor N channels corresponding to N satellites in a global positioningsystem (GPS) receiver; an address counter coupled to the first memory togenerate an address modulo-KN corresponding to a first location in thememory at the first clock frequency; and an adder coupled to the mixerand the first memory to add one of the mixer samples to contents of thefirst location to generate a sum, the sum being written into the firstlocation.
 2. The apparatus of claim 1 further comprising: a secondmemory coupled to the first memory and the address counter to store theK sums of mixer samples transferred from the first memory at end of theepoch interval.
 3. The apparatus of claim 1 further comprising: an epochcontrol circuit to generate an epoch signal indicative of the epochinterval.
 4. The apparatus of claim 3 wherein the epoch control circuitcomprises: N epoch interval generators to generate N channel intervalsignals; a decoder to enable one of the N epoch interval generators; anda multiplexer coupled to the N epoch interval generators to select oneof the N channel interval signals, the selected one of the N channelinterval signals corresponding to the epoch signal.
 5. The apparatus ofclaim 1 wherein K=22 and N=12.
 6. The apparatus of claim 5 wherein thefirst clock frequency is equal to twenty-four times a coarse/acquisitionchip rate of the GPS receiver.
 7. An apparatus comprising: a mixercircuit to mix a de-spreaded sample with coefficients to generate amixer sample at a first clock frequency, the de-spread sample beingprovided by a de-spreader circuit for a signal received from one of Nsatellites in a global positioning system (GPS); a look-up table coupledto the mixer circuit to generate the coefficients based on a carriernumerically controlled oscillator (NCO) value; and a carrier NCO coupledto the look-up table to generate a carrier NCO value.
 8. The apparatusof claim 7 wherein the de-spread sample includes de-spread in-phase andde-spread quadrature components, each component having 6 bits.
 9. Theapparatus of claim 8 wherein the coefficients include a sine and cosinevalues, each value having three bits.
 10. The apparatus of claim 9wherein the mixer sample includes mixer in-phase and quadraturecomponents.
 11. The apparatus of claim 9 wherein the mixer circuitcomprises: an in-phase circuit to generate the mixer in-phase componentbased on a first complex multiplication on the de-spread in-phase andquadrature components and the sine and cosine values, the mixer in-phasecomponent having 8 bits; and a quadrature circuit to generate the mixerquadrature component based on a second complex multiplication on thede-spread in-phase and quadrature components and the sine and cosinevalues, the mixer quadrature component having 8 bits.
 12. The apparatusof claim 7 wherein the carrier NCO comprises: N carrier base circuits togenerate N carrier channel NCO values at a second clock frequency, eachof the N carrier base circuits having an increment register to store anincrement value loaded from a processor; a decoder coupled to the Ncarrier base circuits to enable loading of one of the N incrementregisters based on a channel select value; and a multiplexer coupled tothe N carrier base circuits to select the carrier NCO value from the Ncarrier channel NCO values at the first clock frequency.
 13. Theapparatus of claim 11 wherein N=12.
 14. The apparatus of claim 12wherein the first clock frequency is equal to twenty-four times acoarse/acquisition chip rate of the GPS.
 15. The apparatus of claim 13wherein the second clock frequency is equal to one-quarter times acoarse/acquisition chip rate of the GPS.
 16. A method comprising:storing K sums of mixer samples during an epoch interval, the mixersamples being generated at a first clock frequency from a mixer for Nchannels corresponding to N satellites in a global positioning system(GPS) receiver; generating an address modulo-KN corresponding to a firstlocation in the memory at the first clock frequency; and adding one ofthe mixer samples to contents of the first location, the sum beingwritten into the first location.
 17. The method of claim 16 furthercomprising: storing the K sums of mixer samples transferred from thefirst memory at end of the epoch interval.
 18. The method of claim 16further comprising: generating an epoch signal indicative of the epochinterval.
 19. The method of claim 18 wherein the epoch control circuitcomprises: generating N channel interval signals; enabling one of the Nepoch interval generators; and selecting one of the N channel intervalsignals, the selected one of the N channel interval signalscorresponding to the epoch signal.
 20. The method of claim 16 whereinK=22 and N=12.
 21. The method of claim 20 wherein the first clockfrequency is equal to twenty-four times a coarse/acquisition chip rateof the GPS receiver.
 22. A method comprising: mixing a de-spreadedsample with coefficients to generate a mixer sample at a first clockfrequency, the de-spread sample being provided by a de-spreader circuitfor a signal received from one of N satellites in a global positioningsystem (GPS); generating the coefficients based on a carrier numericallycontrolled oscillator (NCO) value; and generating a carrier NCO value.23. The method of claim 22 wherein the de-spread sample includesde-spread in-phase and de-spread quadrature components, each componenthaving 6 bits.
 24. The method of claim 23 wherein the coefficientsinclude a sine and cosine values, each value having three bits.
 25. Themethod of claim 24 wherein the mixer sample includes mixer in-phase andquadrature components.
 26. The method of claim 24 wherein the mixercircuit comprises: generating the mixer in-phase component based on afirst complex multiplication on the de-spread in-phase and quadraturecomponents and the sine and cosine values, the mixer in-phase componenthaving 8 bits; and generating the mixer quadrature component based on asecond complex multiplication on the de-spread in-phase and quadraturecomponents and the sine and cosine values, the mixer quadraturecomponent having 8 bits.
 27. The method of claim 22 wherein the carrierNCO comprises: generating N carrier channel NCO values at a second clockfrequency, each of the N carrier base circuits having an incrementregister to store an increment value loaded from a processor; enablingloading of one of the N increment registers based on a channel selectvalue; and selecting the carrier NCO value from the N carrier channelNCO values at the first clock frequency.
 28. The method of claim 26wherein N
 12. 29. The method of claim 27 wherein the first clockfrequency is equal to twenty-four times a coarse/acquisition chip rateof the GPS.
 30. The method of claim 28 wherein the second clockfrequency is equal to one-quarter times a coarse/acquisition chip rateof the GPS.
 31. A receiver comprising: a mixer circuit to mixde-spreaded samples with coefficients to generate mixer samples at afirst clock frequency, the de-spread samples being provided by ade-spreader circuit for a signal received from one of N channelscorresponding to N sa tellites in a global positioning system (GPS); acarrier numerically controlled oscillator (NCO) circuit coupled to themixer to generate the coefficients based one of the N channels, the NCOcircuit comprising: a first memory having KN locations to store K sumsof the mixer samples during an epoch interval, an address countercoupled to the first memory to generate an address modulo-KNcorresponding to a first location in the first memory at the first clockfrequency, and an adder coupled to the mixer and the first memory to addone of the mixer samples to contents of the first location, the sumbeing written into the first location.
 32. The receiver of claim 31further comprising: a second memory coupled to the first memory and theaddress counter to store the K sums of mixer samples transferred fromthe first memory at end of the epoch interval.
 33. The receiver of claim31 further comprising: an epoch control circuit to generate an epochsignal indicative of the epoch interval.
 34. The receiver of claim 33wherein the epoch control circuit comprises: N epoch interval generatorsto generate N channel interval signals; a decoder to enable one of the Nepoch interval generators; and a multiplexer coupled to the N epochinterval generators to select one of the N channel interval signals, theselected one of the N channel interval signals corresponding to theepoch signal.
 35. The receiver of claim 31 wherein K=22 and N=12. 36.The receiver of claim 35 wherein the first clock frequency is equal totwenty-four times a coarse/acquisition chip rate of the GPS receiver.37. A receiver comprising: a de-spread circuit to de-spread a sample fora signal received from one of N satellites in a global positioningsystem (GPS); and a Doppler circuit coupled to the de-spread circuit toremove Doppler frequency, the Doppler circuit comprising: a mixercircuit to mix the de-spreaded sample with coefficients to generate amixer sample at a first clock frequency; a look-up table coupled to themixer circuit to generate the coefficients based on a carriernumerically controlled oscillator (NCO) value; and a carrier NCO coupledto the look-up table to generate a carrier NCO value.
 38. The receiverof claim 37 wherein the de-spread sample includes de-spread in-phase andde-spread quadrature components, each component having 6 bits.
 39. Thereceiver of claim 38 wherein the coefficients include a sine and cosinevalues, each value having three bits.
 40. The receiver of claim 39wherein the mixer sample includes mixer in-phase and quadraturecomponents.
 41. The receiver of claim 39 wherein the mixer circuitcomprises: an in-phase circuit to generate the mixer in-phase componentbased on a first complex multiplication on the de-spread in-phase andquadrature components and the sine and cosine values, the mixer in-phasecomponent having 8 bits; and a quadrature circuit to generate the mixerquadrature component based on a second complex multiplication on thede-spread in-phase and quadrature components and the sine and cosinevalues, the mixer quadrature component having 8 bits.
 42. The receiverof claim 37 wherein the carrier NCO comprises: N carrier base circuitsto generate N carrier channel NCO values at a second clock frequency,each of the N carrier base circuits having an increment register tostore an increment value loaded from a processor; a decoder coupled tothe N carrier base circuits to enable loading of one of the N incrementregisters based on a channel select value; and a multiplexer coupled tothe N carrier base circuits to select the carrier NCO value from the Ncarrier channel NCO values at the first clock frequency.
 43. Thereceiver of claim 41 wherein N=12.
 44. The receiver of claim 42 whereinthe first clock frequency is equal to twenty-four times acoarse/acquisition chip rate of the GPS.
 45. The receiver of claim 43wherein the second clock frequency is equal to one-quarter times acoarse/acquisition chip rate of the GPS.